The delay of synchronous logic nets

Abstract

The delay of networks of delayed-logic synchronous devices is considered in this paper. In particular, the paper is concerned with the delay of representations of Boolean functions constructed from unit delay logic devices. It is shown that the delay required for some non-zero fraction of functions represented grows linearly with the number of arguments (input sequences). It is also shown that this fraction gets extremely large as the number of arguments grows. It is demonstrated that a simple construction technique used with AND, OR, and NOT devices with unit delay can produce networks with delays that also grow linearly in delay as a function of number of arguments with the same slope.