Parallel software-based self-test suite for multi-core system-on-chip: Migration from single-core to multi-core automotive microcontrollers

Abstract

In recent years the complexity of System-On-Chips have been grown exponentially, mainly due to the ever-increasing demand for more functionalities, even for embedded applications. In order to fulfil such requests, semiconductor vendors introduced in this market multi-core devices. However, despite the gain in terms of performance, the adoption of multi-core devices pose several issues from the testing viewpoint. In particular, it is required to evolve the in-field testing strategies (commonly used to increase the reliability level of a processor-based system) from the single-core to the multi-core case. In this paper, we present a possible approach for rapidly migrating a Software Test Library, developed according the Software-Based Self-Test approach for a single-core processor, to a multi-core processor. The proposed methodology relies on the usage of hardware semaphores in order to reduce memory utilization and control the access to shared resources among different cores. The experimental results were performed on a multi-core microcontroller manufactured by STMicroelectronics.