Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©

Abstract

Multiple Valued Logic (MVL) has been gaining popularity and practical applications. In addition to the standard MVL benefits, quaternary logic offers the benefit of easy interfacing to binary logic due to the fact that the radix 4=22 allows for simple encoding/decoding circuits. Quaternary cells based on the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) [2] are modeled and used for our adder circuit structures. Several different adder configurations are designed and modeled using the basic quaternary gates and are modeled with the SystemVerilog modeling language. Different adder configurations are compared for their size and estimated logic depth for area and performance estimation and compared with their binary counterparts.