Evaluating Memory Performance of Emerging Scale-Out Applications Using C-AMAT

Abstract

Modern dominant processor architectures that emphasize high single-thread performance and deep memory hierarchy mismatch the needs of emerging scale-out workloads. Understanding these inefficiencies, especially inefficiencies in memory systems is important for high efficient architecture design. In this paper, we evaluate the memory performance of emerging scale-out applications using a newly proposed memory metric, C-AMAT. We find that scale-out applications suffer more from current memory hierarchy compared to traditional server workloads and desktop benchmarks, especially in terms of memory access concurrency in L1 data cache and L2 cache. Suggestions are provided to improve their memory performance , including adopting designs like multi-port, multi-banked cache, setting appropriate number of MSHRs and applying advanced data prefetchers.