A novel NMOS transistor for high performance ESD protection devices in 0.18 /spl mu/m CMOS technology utilizing salicide process

Abstract

The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTs consisting of dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, and HBM and machine model (MM) robustness. The state-of-the-art 0.18 /spl mu/m cobalt salicide CMOS process is used, and the thickness of the gate dielectric material is 35 /spl Aring/. Fully salicided ggNMOSTs have much lower values of second breakdown current (It2) than partially salicided ggNMOSTs, and with multi-finger structures, only partially salicided ggNMOSTs turn on uniformly. Using these partially salicided NMOSTs as protection devices, we acquired ESD immunity of >2 kV (HBM) and >200 V (MM).