Run-Time Reconfigurable System-on-Chip

Abstract

This paper introduces a novel architecture that is targeted for adaptive embedded system applications, such as telerobotics, space navigation and wireless hot-spot access points. All these applications consist of static (i.e. known) hard and soft realtime constraints, as well as dynamic (i.e. unknown and unpredictable) environment conditions, hence require the predictability of fixed hardware resources, along with the adaptability of programmable hardware devices. The proposed embedded system consists of a soft-core fixed microprocessor and a reconfigurable co-processor. The latter utilizes Run-Time Reconfiguration (RTR) functionality in order to respond to the changing environment inputs, while the former guarantees meeting soft and hard deadlines in order to achieve the intended system functionality. The Reconfigurable Processor Unit (RPU) allows for the simultaneous execution of multiple hardware functional units, by exploiting a Just-In-Time (JIT) compiler in order to maintain hardware and software flow synchronization. However, the JIT compiler description is outside the scope of this paper