A Comparison of DAG and Mesh Topologies for Coarse-Grain Reconfigurable Array

Abstract

In this paper, we address the hardware overhead of the dynamically reconfigurable functional unit (DRFU) in dynamically reconfigurable processors (DRP), in the context of low-power, embedded system-on-chips (E-SoC). We consider a tightly coupled DRP with a small, coarse-grain DRFU made of four columns of four ALUs. These are interconnected following one of the following interconnection scheme: direct acyclic graph or mesh. Given a large set of of custom instructions to map on the DRFU, we explore the simplification opportunities on the DRFU in order to reduce its hardware cost. We determine that it is possible to reduce its footprint by about 70 % with respect to the ALUs for both topologies and 50 % with respect to the interconnection between ALUs. We also provide the place and route algorithm to achieve these results. At the end of the paper we compare both topologies with respect to the hardware usage, the opportunities for simplifications and the complexity of the place and route algorithm. We conclude that the mesh topology is in all the cases the most desirable.