Fine grain thread scheduling on multicore processors: cores with multiple functional units

Abstract

The proposed work discusses a global scheduling technique for multicore processors with specific focus on processor cores having multiple functional units. The design philosophy of the multicore architecture is to accommodate more cores with more execution capabilities on a chip by reducing other complex and redundant circuits. Due to the simplicity of hardware on the chip of multicore processor, the onus of detecting and exploiting the instruction level parallelism (ILP) in the program lies on the complier. Following work proposes a scheduling technique which is used to schedule the instructions onto multiple cores on chip each having multiple functional units. The goal is achieved by dissecting each basic block of the program's control flow graph (CFG) into sub-divisions called sub-blocks. These sub-blocks are then analyzed for the break-up of instructions on the basis of instruction type (Integer or Floating Point) and then they are scheduled onto different cores while trying to get a balanced trade-off between communication costs amongst the cores. The scheduler provides enough or approximately equal number of integer and floating point instructions to each core which may be executed in parallel on the core's multiple functional units (integer unit and floating point units), thus taking advantage of the core's architecture.