Very Massive Hardware Merge Sorter

M. Saitoh, Kenji Kise
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引用次数: 8

Abstract

The state-of-the-art hardware merge sorter called MMS has the tie-record issue that the records having the same key can cause the problem. MMS solves this issue by inefficient scheme comparing both key and satellite data fields of records to determine whether two records are swapped or not. We propose a high-performance hardware merge sorter (VMS) which adopts an efficient solution to the issue comparing just key fields. We also present the detailed circuit of VMS that adopts some implementation optimizations. We implement and evaluate VMS on a Virtex-7 FPGA. The evaluation results show that our proposed merge sorter requires fewer hardware resources and achieves 1.44x better throughput than MMS when large records are used.
非常庞大的硬件合并排序器
称为MMS的最先进的硬件合并排序器有一个并列记录问题,即具有相同键的记录可能导致问题。MMS通过比较记录的关键字段和卫星数据字段来确定两个记录是否交换,从而解决了这个问题。本文提出了一种高性能的硬件归并排序器(VMS),它有效地解决了关键字段的比较问题。本文还详细介绍了VMS的电路,并对其实现进行了优化。我们在Virtex-7 FPGA上实现和评估了VMS。评估结果表明,当使用大量记录时,我们提出的合并排序器需要更少的硬件资源,并且实现了比MMS高1.44倍的吞吐量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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