Implementation of a Dual-core 64-bit RISC-V on 7nm FinFET Process

Abstract

This paper presents a back-end implementation of a Dual-core 64-bit RISC-V using the proposed digital ASIC design flow with hardware construction language Chisel. A design flow started from the Chisel code of Dual-core 64-bit RISC-V generated from Chipyard. After that, Verilog source code was converted from Chisel with the configured Dual-core 64-bit RISC-V architecture. This design was successfully implemented on TSMC 7nm FinFET process with the proposed ASIC design flow and design techniques for complex CPU designs. The Dual-core 64-bit RISC-V has a core size of 1.17 x 1.17mm, operating at maximum frequency 500MHz, and consuming power 493.7mW.