A Two-step SAR ADC with Synchronous DEM Calibration Achieving Up to 15% Power Reduction

Zhechong Lan, Li Dong, Xixin Jing, Liheng Liu, Ken Li, Ziyan Shen, Zhiming Li, Li Geng
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引用次数: 2

Abstract

This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.
具有同步DEM校准的两步SAR ADC实现高达15%的功耗降低
本文提出了一种采用同步动态元素匹配(DEM)算法校准的两步12位连续逼近寄存器(SAR)模数转换器(ADC)。在本文提出的两步结构中,在某些转换周期内用低功耗比较取代了高精度比较,从而降低了ADC的功耗。DEM校准非常适合两步结构,并在可忽略的额外功率损失下实现一阶不匹配整形。所提出的SAR ADC采用标准的180 nm CMOS技术制造,核心面积为0.226 mm2。采样率为200ks /s时,功耗为9.15 μW,功耗降低15%,SNDR为68.85 dB。所得的优值(FoM)为20.13 fJ/转换步。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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