Zhechong Lan, Li Dong, Xixin Jing, Liheng Liu, Ken Li, Ziyan Shen, Zhiming Li, Li Geng
{"title":"A Two-step SAR ADC with Synchronous DEM Calibration Achieving Up to 15% Power Reduction","authors":"Zhechong Lan, Li Dong, Xixin Jing, Liheng Liu, Ken Li, Ziyan Shen, Zhiming Li, Li Geng","doi":"10.1109/APCCAS50809.2020.9301655","DOIUrl":null,"url":null,"abstract":"This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS50809.2020.9301655","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.