A Two-step SAR ADC with Synchronous DEM Calibration Achieving Up to 15% Power Reduction

Abstract

This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.