Cost aware task scheduling and core mapping on Network-on-Chip topology using Firefly algorithm

Abstract

An optimal Network on Chip topology is generated with reduced area and power consumption. The Firefly algorithm is used for the optimal mapping of each and every Intellectual Property core in a specific application. This method incorporates multiple objectives subject to some constraints based on the information available in the Communication Task Graph. The paper proceeds with two phases. In the first phase the tasks are mapped on the processors and in the second phase the processors are mapped on the network tiles.