Ultrahigh speed transceiver package with stacked silicon integration technology

Abstract

As carrier frequency going into millimeter wave domain, today's semiconductor IC package enters a domain where many challenges become fundamental to legacy technology and design practice. In this study, we analyze interconnect impairment for ultrahigh speed transceivers. To answer the challenge towards 56Gbps, we assess system compensation schemes from silicon equalization to passive interconnect innovations. The author will specifically address recent advancement in stacked silicon integration technology (SSIT) and its role in 400G/1TB system solutions.