Reducing the number of transistors with gate clustering

Abstract

In this work a greedy cell clustering technique is proposed to reduce the number of transistors of circuits. Reducing the amount of transistors can provide leakage power reduction. The clusterization is applied to a set of connected cells with fanout one. These cells are replaced by a equivalent logic complex cell. Hereafter, the layout of any cluster can be automatically designed by using a layout generation tool. The ITC'99 benchmark circuits are synthesized to the 45nm Open Cell Library. The clustering technique presented in this work is able to provide a reduction in the number of transistors of 9.8%, on average, over the synthesis using all cells available in the library. We show that the set of logic functions used by the input netlist influences the results obtained by clustering. For a netlist synthesized without the complex cells of the library our clustering technique reduced the number of transistors in up to 22.3% when compared to the original netlist.