Compact (Wg/Lg=80/85nm) FDSOI 1T-DRAM programmed by Meta Stable Dip

Abstract

We demonstrate one of the most compact 1 Transistor DRAM (1T-DRAM) cell on Ultra-Thin-Body and 25nm thin Buried oxide (UTBB) down to a gate width of Wg=80nm and length of Lg=35nm for embedded DRAM applications. We have optimized the programming voltages and studied the influence of the device geometry (Wg, Lg) on the 1T-DRAM performance. The Meta Stable Dip (MSD) method provides high read current margin values, reaching 224μA/μm. This is the first experimental assessment of the MSD approach on such scaled 1T-DRAMs.