Tie Wang, T. H. Chew, C. Lum, Y. Chew, P. Miao, L. Foo
{"title":"Assessment of flip chip assembly and reliability via reflowable underfill","authors":"Tie Wang, T. H. Chew, C. Lum, Y. Chew, P. Miao, L. Foo","doi":"10.1109/ECTC.2001.927875","DOIUrl":null,"url":null,"abstract":"This paper presents process concerns of flip-chip assembly via reflowable underfill in terms of substrate prebake, underfill dispensing, chip placement and overmolding that is required in certain applications. Test vehicles with various chip configurations and substrate design have been used in this study. The effects of substrate thickness, bond pad design and solder mask thickness on assembly defects, where void is the major contribution, were extensively elucidated. Meanwhile, approaches to solve the assembly failure have been successfully demonstrated by means of fine-tuning assembly parameters. It was found that voids were mainly from trapped air-bubbles during assembly, where underfill dispensing and chip placement are the major sources, rather than from reflowable underfill outgassing during reflow. The trapped voids could become aggravated after solder reflow process. In addition, pad design and solder mask thickness also significantly affect the void level. This study unveils that substrate bond pad with pre-solder on the surface traps less void than those only with nickel gold finish. For the latter case, substrate heating during underfill dispensing enables to enhance underfill flow and in turn reduces void. Furthermore, die heating that can be implemented via bonding head with heating element during chip placement will dramatically reduce void as well. Discussion will also be given on the impact of solder mask thickness and chip placement; speed (search speed) on void, in particularly for non pre-solder capped substrate.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"29 24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2001.927875","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
This paper presents process concerns of flip-chip assembly via reflowable underfill in terms of substrate prebake, underfill dispensing, chip placement and overmolding that is required in certain applications. Test vehicles with various chip configurations and substrate design have been used in this study. The effects of substrate thickness, bond pad design and solder mask thickness on assembly defects, where void is the major contribution, were extensively elucidated. Meanwhile, approaches to solve the assembly failure have been successfully demonstrated by means of fine-tuning assembly parameters. It was found that voids were mainly from trapped air-bubbles during assembly, where underfill dispensing and chip placement are the major sources, rather than from reflowable underfill outgassing during reflow. The trapped voids could become aggravated after solder reflow process. In addition, pad design and solder mask thickness also significantly affect the void level. This study unveils that substrate bond pad with pre-solder on the surface traps less void than those only with nickel gold finish. For the latter case, substrate heating during underfill dispensing enables to enhance underfill flow and in turn reduces void. Furthermore, die heating that can be implemented via bonding head with heating element during chip placement will dramatically reduce void as well. Discussion will also be given on the impact of solder mask thickness and chip placement; speed (search speed) on void, in particularly for non pre-solder capped substrate.