Yuru Wang, G. Lyu, Jin Wei, Zheyang Zheng, Kailun Zhong, K. J. Chen
{"title":"All-WBG Cascode Device with p-GaN Gate HEMT and SiC JFET for High-Frequency and High-Temperature Power Switching Applications","authors":"Yuru Wang, G. Lyu, Jin Wei, Zheyang Zheng, Kailun Zhong, K. J. Chen","doi":"10.1109/WiPDAAsia49671.2020.9360291","DOIUrl":null,"url":null,"abstract":"An all-wide-bandgap (all-WBG) cascode device with a low-voltage (LV) enhance-mode (E-mode) p-GaN gate HEMT as the control device and a high-voltage (HV) depletion-mode (D-mode) SiC JFET as the voltage blocking device has been systematically studied. The demonstrated device with a breakdown voltage (BV) rating of 1200 V and a static ON-resistance (RON) of 100 m$\\Omega$, features small device capacitances, avalanche breakdown capability, thermally stable threshold voltage (VTH), no dynamic RON degradation, and small gate charge (QG). To identify its safe operation in the OFF-state with a high drain bias, the OFF-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. An adequately low OFF-state VMis achieved under both static and dynamic modes. Furthermore, a double-pulse test circuit is built to evaluate the transient switching performance at $25^{\\circ}C$ and $150^{\\circ}C$. Under 800-V/16-A testing conditions, high switching speed with low total switching losses of $214 \\mu J$ and $236 \\mu J$ are obtained at $25^{\\circ}C$ and $150^{\\circ}C$, respectively.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360291","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An all-wide-bandgap (all-WBG) cascode device with a low-voltage (LV) enhance-mode (E-mode) p-GaN gate HEMT as the control device and a high-voltage (HV) depletion-mode (D-mode) SiC JFET as the voltage blocking device has been systematically studied. The demonstrated device with a breakdown voltage (BV) rating of 1200 V and a static ON-resistance (RON) of 100 m$\Omega$, features small device capacitances, avalanche breakdown capability, thermally stable threshold voltage (VTH), no dynamic RON degradation, and small gate charge (QG). To identify its safe operation in the OFF-state with a high drain bias, the OFF-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. An adequately low OFF-state VMis achieved under both static and dynamic modes. Furthermore, a double-pulse test circuit is built to evaluate the transient switching performance at $25^{\circ}C$ and $150^{\circ}C$. Under 800-V/16-A testing conditions, high switching speed with low total switching losses of $214 \mu J$ and $236 \mu J$ are obtained at $25^{\circ}C$ and $150^{\circ}C$, respectively.