AREAL: automated reasoning expert for analogue layout

Abstract

A system for analogue circuit layout generation is presented which utilises knowledge and geometric reasoning to prune the design space. Topological and geometric constraints, deduced from analogue and connectivity information, are expressed in the form of Boolean relations, and are imposed and preserved throughout the solution by means of a Boolean-constraint-solver. The reduced design space is then explored by a controlled branch-and-bound process to find an optimal solution.<>