Recursively scalable fat-trees as interconnection networks

Abstract

We introduce orthogonal fat-trees as a type of interconnection network for parallel computers, and show how they can be used to maximize the number of processors in a massively parallel computer when the degree of the internal nodes and the diameter of the network are physically constrained. The basic building block of these orthogonal fat-trees is a two-level fat-tree that is obtained from a complete set of mutually orthogonal Latin Squares. As a practical application of orthogonal fat-trees, we propose a new interconnection network for a massively parallel computer based on the QROOOl Data Stream Controller Interface, an integrated circuit produced by National Semiconductor, which can sustain a throughput of up to 180 MBytes/sec. The network consists of multiple interconnected rings and is constrained to have at most 16 nodes per ring and a maximum diameter of four. Our solution yields a maximum of 51,984 processors.