SoC design case study using SystemC specifications

Abstract

Modern systems become more and more complex and tendency turn to the integration on one single chip: System on Chip (SoC). A major constraint consists of "Time-to-Market". Hence, the emergence of SoC is creating many new challenges, especially, the necessity of a unified language for the system level design. SystemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware / software systems. This paper describes a method of stepwise refinement with SystemC, starting from an algorithmic description and progressively adding implementation details. The method is described with reference to a Turbo encoder, which is progressively moved from a purely abstract level to a more detailed description. This study is realized to emphasize on the importance of this tendency within the framework of SoC design. We also present the experimental results from specification, refinement and validation with SystemC and simulation effectiveness of the proposed method.