Emitter coupled logic and cascode current switch testability and design for test

Abstract

Application-specific integrated circuits (ASICs) are frequently utilized in applications demanding the highest circuit performance. Gate delays under 300 ps are now achievable using emitter coupled logic (ECL) and cascode current switch (CCS). However, as performance increases, so does the difficulty and cost of testing for quality parts. The design and operation of ECL and CCS and their sensitivities to chip failure mechanisms are discussed. By applying DC-level shifts to the internal signals, these faults can become testable. An approach to the design and test of these gates which enhances the testability of both AC and DC defects is given.<>