Boosting CPU Performance using Pipelined Branch and Jump Folding Hardware with Turbo Module

Abstract

The new generation of embedded applications demands both high performance and energy efficiency. This paper presents a new hardware design to support architecture-level thread isolation, together with logics to fold the branch and jump instructions and a Turbo module, thereby reducing the overall number of instructions flowing through the CPU without causing any pipeline stalls. By pipelining the branch and jump folding logics from multiple threads of execution, the hardware can continuously operate at the peak CPU speed, with reduced power consumption by reducing the number of microcontrollers required in the system. We show that this novel technique can accelerate the system performance, increase the instruction per cycle up to 1.36, and with the Turbo module, up to 1.823, without requiring any extra programming effort by developers. We used the Dhrystone, Coremark, and ten selected benchmark metrics to validate the performance and functionality of our system.