The impact of out-of-order message delivery on cache coherence protocols

Abstract

The opimizations of the communication controller improve the overall performance of a distributed shared memory (DSM) system, but also make the out-of-order message delivery possible which can lead to deadlock situations, The goal of the paper is to propose the solution for preventing the deadlock and to evaluate the performance for a real workload. First, the basic cache coherence protocol was adopted and the actions implied by the directory data access model, requirements for a relaxed memory consistency model, and network and controller delays are also defined. After that, the critical situations are clearly identified. Then, a solution for deadlock avoidance, which uses two-bit counters for rejected acknowledgement messages, is proposed. The simulation analysis with the representative SPLASH-2 real benchmark suite was carried out to evaluate the overall performance. Finally, the results of the analysis are presented and discussed for different system parameter values.