High-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM

Abstract

This paper describes high-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM. Several 1 V operating SRAMs have been reported so far, but none of them achieves both fast access time of 200 ns at 1 V and low standby power below O.1 /spl mu/W under 1-3 V range compatibly. This 1Mb SRAM is designed to achieve the performance above, which is suitable for both 1.5 V battery-operational application and 3 V use. Several circuit techniques such as Multi-Vth CMOS gates, Switched Delay-Line Pulse Generator ( SDLPG) and Resistor-inserted Current mirror sense Amplifier (RCSA) have been developed.