VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture

Abstract

This paper proposes a novel architecture for highspeed RSA crypto-processor with reconfigurable architecture. Through analysing and comparing between the original algorithms with modified Modular exponentiation and Montgomery multiplication algorithm, a nested pipelined RSA crypto-processor architecture is presented. Based on this architecture, we can easily design a RSA crypto-processor with various speed & key length, it is very flexible to design an encrypt IP core in the SOC platform. As an example, a 1024-bit, 5Mbps RSA cryptoprocessor is implemented. The result shows that the architecture proposed by this paper is practical and efficient.