A 1 GHz 1.8 V monolithic CMOS PLL with improved locking

Abstract

A 1 GHz 1.8 V monolithic CMOS phase-locked loop (PLL) circuit for high-speed serial bus applications is presented. The monolithic PLL consists of a dead-less phase frequency detector, a charge pump, a bias generator circuit with an auxiliary bias generator to secure locking, a voltage-controlled oscillator and a differential to single-ended converter with duty cycle correction. A startup circuit is added to prevent the PLL from false locking and to expedite the locking. The PLL has been fabricated in a 0.18 /spl mu/m CMOS technology, occupying an active area of 0.02 mm/sup 2/. The PLL can operate from 100 MHz up to 1.2 GHz and consumes less than 10 mW from a 1.8 V supply.