Jacinta Aman Lim, Yun-Mook Park, Edil De Vera, Byung-Cheol Kim, B. Dunlap
{"title":"600mm Fan-Out Panel Level Packaging (FOPLP) As A Scale Up Alternative to 300mm Fan-Out Wafer Level Packaging (FOWLP) with 6-Sided Die Protection","authors":"Jacinta Aman Lim, Yun-Mook Park, Edil De Vera, Byung-Cheol Kim, B. Dunlap","doi":"10.1109/ECTC32696.2021.00174","DOIUrl":null,"url":null,"abstract":"The need for migrating to carrier sizes larger than 300mm becomes a necessity to lower down costs and handle higher volumes. As the demand for PMICs, RF and other single die applications increases for Fan-Out Wafer Level Packaging (FOWLP) processing on mainstream carrier sizes, large Panel Level Processing to meet these demands become a natural progression to an already burgeoning market. However, not all products would benefit from migrating from 300mm/330mm carrier to large panel. If the total area of the panel is not fully utilized, it results in material waste and loss. While FOWLP has been established as one of the most versatile packaging technologies in the recent past and already accounts for over $1.2 billion USD due to its unique advantages, traditional 300mm round carrier used for processing FOWLP is still cost inhibitive. This paper will present the background of utilizing $\\mathrm{600}\\text{mm}\\times \\mathrm{600}\\text{mm}$ square panel size and show an example of leveraging from existing equipment for backend processing for cost considerations. We will also review the processing method for 6-sided die protection of a single die and how it translates to $\\mathrm{600}\\text{mm}\\times \\mathrm{600}\\text{mm}$ square panel processing. Comparisons between usable area of 300mm round carrier versus $\\mathrm{600}\\text{mm}\\times \\mathrm{600}\\text{mm}$ square panel, sweet spot recommendation for pricing per unit based on body size and Component Level Reliability (CLR) will be presented.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"433 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC32696.2021.00174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The need for migrating to carrier sizes larger than 300mm becomes a necessity to lower down costs and handle higher volumes. As the demand for PMICs, RF and other single die applications increases for Fan-Out Wafer Level Packaging (FOWLP) processing on mainstream carrier sizes, large Panel Level Processing to meet these demands become a natural progression to an already burgeoning market. However, not all products would benefit from migrating from 300mm/330mm carrier to large panel. If the total area of the panel is not fully utilized, it results in material waste and loss. While FOWLP has been established as one of the most versatile packaging technologies in the recent past and already accounts for over $1.2 billion USD due to its unique advantages, traditional 300mm round carrier used for processing FOWLP is still cost inhibitive. This paper will present the background of utilizing $\mathrm{600}\text{mm}\times \mathrm{600}\text{mm}$ square panel size and show an example of leveraging from existing equipment for backend processing for cost considerations. We will also review the processing method for 6-sided die protection of a single die and how it translates to $\mathrm{600}\text{mm}\times \mathrm{600}\text{mm}$ square panel processing. Comparisons between usable area of 300mm round carrier versus $\mathrm{600}\text{mm}\times \mathrm{600}\text{mm}$ square panel, sweet spot recommendation for pricing per unit based on body size and Component Level Reliability (CLR) will be presented.