{"title":"Resistorless electronically tunable grounded inductance simulator design","authors":"N. Herencsar, A. Kartci","doi":"10.1109/TSP.2017.8075987","DOIUrl":null,"url":null,"abstract":"A new realization of grounded lossless positive inductance simulator (PIS) using simple inverting voltage buffer and unity-gain current follower/inverter (CF±) is reported. Considering the input intrinsic resistance of CF± as useful active parameter, the proposed PIS can be considered as resistorless circuit and it only employs in total 16 Metal-Oxide-Semiconductor (MOS) transistors and a grounded capacitor. The resulting equivalent inductance value of the proposed simulator can be adjusted via change of input intrinsic resistance of CF± by means of its supply voltages. The behavior of the proposed simulator circuit is tested via implementation in voltage-mode 5th-order high-pass filter RLC prototype with Bessel, Butterworth, and Chebyshev I approximation. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±0.9 V supply voltages.","PeriodicalId":256818,"journal":{"name":"2017 40th International Conference on Telecommunications and Signal Processing (TSP)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 40th International Conference on Telecommunications and Signal Processing (TSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TSP.2017.8075987","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A new realization of grounded lossless positive inductance simulator (PIS) using simple inverting voltage buffer and unity-gain current follower/inverter (CF±) is reported. Considering the input intrinsic resistance of CF± as useful active parameter, the proposed PIS can be considered as resistorless circuit and it only employs in total 16 Metal-Oxide-Semiconductor (MOS) transistors and a grounded capacitor. The resulting equivalent inductance value of the proposed simulator can be adjusted via change of input intrinsic resistance of CF± by means of its supply voltages. The behavior of the proposed simulator circuit is tested via implementation in voltage-mode 5th-order high-pass filter RLC prototype with Bessel, Butterworth, and Chebyshev I approximation. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±0.9 V supply voltages.