Novel CNFET SRAM cell design operating in sub-threshold region using back-gate biasing

Abstract

This paper proposes a new design of carbon nanotube FETs (CNFETs) based SRAM cell operating in subthreshold region. By using optimum back-gate biasing scheme for each transistor, the proposed SRAM cell achieves the best overall performance considering noise margin, delay and power. Compared with traditional subthreshold CNFET SRAM cell, the proposed SRAM cell increases static voltage noise margin (SVNM) 36%, increases static current noise margin (SINM) 2.5X, and reduces delay 61% with power consumption increasing only 1% for read operation. For write operation, the proposed SRAM cell increases write noise margin (WNM) 2.5X and reduces power consumption and delay 17% and 56% respectively compared with traditional subthreshold CNFET SRAM cell. In terms of total number of nanotubes (area) of CNFET SRAM cell, the proposed subthreshold CNFET SRAM cell can reduce at least half of total number of nanotubes without compromising noise margin, power and delay. New CNFET SRAM cell structure is proposed to dynamically bias each transistor at different operation modes.