Minimum delay switch for Synchronous TDMA network

Abstract

Minimum delay Ethernet switch was designed and implemented to construct Synchronous TDMA network. To minimize packet forwarding delay, a novel signal forwarding technique is introduced. The goal of this paper is realizing smaller delay than previous software based S-TDMA switch. The first point is discussion about some factors of delay and design to reduce them. In general, cut-through switch realizes shorter delay than store and forward switch. The proposed technique can realize shorter delay than cut-through switch in principle. To realize shorter delay, this paper proposed an implementation on FPGA boards. In addition, developing measurement equipment using FPGA and comparison between usual switch are also conducted. Experimental results of implemented hubs showed five times shorter delay and smaller jitter than usual software based implementation and other Ethernet switches. The maximum delay to transmit packet through each implemented switch in this paper was 400ns. This implement achieved low maximum delay of 1744ns and jitter of 40ns in 5-hops network. At the end of this paper, discussion about other delay factors and its affect to S-TDMA performance are also concluded.