Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

Abstract

We present a time-efficient lower bound $\tilde \sigma $ on the number of gates in Toffoli-based reversible circuits that represent a given reversible logic function. For the characteristic vector s of a reversible logic function, the value of $\tilde \sigma ({\mathbf{s}})$ is almost the same as σ-lb (s), which is known as a relatively-efficient lower bound in terms of the evaluation time and the tightness. By slightly sacrificing the tightness of the lower bound, $\tilde \sigma $ achieves fast computation. We prove that $\tilde \sigma $ is a lower bound on σ-lb. Next, we show $\tilde \sigma $ can be calculated faster than σ-lb. The time complexity of $\tilde \sigma ({\mathbf{s}})$ is О(n2), where n is the dimension of s. Experimental results to compare $\tilde \sigma $ and σ-lb are also given. The results demonstrate that the values of $\tilde \sigma ({\mathbf{s}})$ are equal to those of σ-lb (s) for most reversible functions and that the computation time of $\tilde \sigma ({\mathbf{s}})$ is much shorter than that of σ-lb(s).