A 5 GHz low-power, high-linearity low-noise amplifier in a digital 0.35 /spl mu/m CMOS process

Abstract

A 5 GHz low noise amplifier (LNA), intended for use in a wireless local area network (WLAN) receiver, has been implemented in a standard digital 0.35 /spl mu/m CMOS process. The amplifier provides a power gain of 9.0 dB while consuming 11 mW from a 2.2 V supply and reaches 6.0 dBm at third order input intermodulation intercept point (IIIP3). In this paper, we present a brief analysis of the LNA architecture and experimental results.