Impact of NoFPGA IP router architecture on link bandwidth

Abstract

In todaypsilas world of advanced technology numerous applications are computationally intensive. This created an opportunity for the development of new system-on-chip (SoC) design techniques to allow easy IP cores (intellectual property cores) re-use and integration under time-to-market pressure. A wide range of these newly emerging design platforms is now drifting towards highly integrated system-on-chip designs with many on-chip processing resources like processors, DSPs, and memories. Using this technique, designers can build system-on-chip (SoC) by integrating dozens of IP cores. As the number of IP cores integrated on a chip increases, the on-chip communication and physical interconnections become a bottleneck. New system-on-chip (SoC) design techniques are necessary to address the communication requirements for future SoC. New communication architecture, the NoFPGA (network-on-FPGA), for future SoFPGA (system-on-FPGA) has been presented. The paper details the architecture of a NoFPGA router. The interconnecting issues in SoFGPA design methodology built in a single FPGA device are addressed. Mainly, the performance analysis of the IPRouter of both torus and mesh topologies is addressed.