Modeling and Design of a Synchronous Reference Frame Enhanced Phase Locked Loop

Abstract

Phase Locked Loops (PLL) are widely used for phase synchronization of two or more than two signals. In power electronics and drives applications, various control schemes are developed in synchronously rotating frame and PLL are used for synchronization of different control units. An Enhanced Phase Locked Loop (EPLL) is an improved structure of conventional PLL. This paper presents the detailed mathematical modeling and design of EPLL in synchronous reference frame. Design based on mathematical modeling is verified through simulation results in this work. Such detailed mathematical model and design is not available in literature which can be very helpful for power electronics and drives applications.