A New and Efficient Algorithm for FPGA Routing

Abstract

In this paper, we propose a new and efficient hybrid Routing algorithm for FPGAs by integrating a Boolean satisfiability algorithm with geometric routing algorithm. It takes advantage of the rip-up-reroute capabilities of the conventional geometric routing algorithm and simultaneous net embedding characteristic of Boolean SAT-based FPGA routing. Experiment results show that compared with the corresponding pure geometric routing algorithm, the running time is dramatic reduced.