Integrated electro-chemical mechanical planarization (Ecmp) for future generation device technology

L. Economikos, X. Wang, X. Sakamoto, P. Ong, M. Naujok, R. Knarr, L. Chen, Y. Moon, S. Neo, J. Salfelder, A. Duboust, A. Manens, W. Lu, S. Shrauti, F. Liu, S. Tsai, W. Swart
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引用次数: 24

Abstract

A novel copper (Cu) planarization process, Ecmp, integrating electro-chemical mechanical polishing capability on a 300mm CMP platform with low down force conventional polishing processes is being developed and evaluated on low-k CVD devices. In the integrated Ecmp process, the bulk Cu is removed by electro-chemical mechanical polishing at a high rate which is controlled by applied charge and is independent of down force (0.3psi bulk Cu removal step). The Ecmp process removes topography efficiently and produces a thin planarized Cu film across the wafer to match that of the conventional Cu planarization step. The Cu thickness profile produced by electro-chemical planarization allows the conventional planarization process to clear remaining Cu with low dishing across the wafer. Therefore, an excessive dielectric removal for dishing correction is not required, making the process extendible to ultra-low k dielectrics that require a protective capping layer to be retained after polishing. Experiments are conducted to evaluate the planarization efficiency, film profile, and endpoint control, cost of consumables, pattern density sensitivity and defect density. The mechanical and electrical results indicate that Ecmp enables the planarization of dual damascene structures with minimal dielectric erosion and defect density.
集成电化学机械平面化(Ecmp)下一代设备技术
一种新型的铜(Cu)平面化工艺,Ecmp,在300mm CMP平台上集成了电化学机械抛光能力和低下压力传统抛光工艺,正在低k CVD器件上进行开发和评估。在集成Ecmp工艺中,大块铜通过电化学机械抛光以高速率去除,该速率由施加的电荷控制,与下压力(0.3psi大块铜去除步骤)无关。Ecmp工艺有效地去除了地形,并在晶圆上产生了一层薄的平坦化Cu膜,以匹配传统的Cu平坦化步骤。电化学平面化产生的Cu厚度剖面允许传统的平面化工艺以低盘面在晶圆上清除剩余的Cu。因此,不需要去除过多的介电以进行碟形校正,使该工艺可扩展到抛光后需要保留保护盖层的超低k介电材料。实验评估了平面化效率、薄膜轮廓和端点控制、耗材成本、图案密度灵敏度和缺陷密度。力学和电学结果表明,Ecmp可以在最小的介电侵蚀和缺陷密度的情况下实现双阻尼结构的平面化。
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