A novel sub ADC architecture for time interleaved

Abstract

This paper studies the sub ADC of time interleaved architecture commonly used in ultra-high speed ADC. Aiming at the shortcomings of pipeline ADC and successive approximation ADC, a two-stage sub ADC architecture combining pipeline ADC and successive approximation ADC is proposed. The rationality of the architecture is verified by Simulink modeling. This architecture combines the advantages of the two kinds of ADC, and improves the performance of single sub ADC and provides a new direction for the selection of sub ADC in time interleaved architecture.