A 200 MSPS reconfigurable ADC with adjacent channel narrowband blocker resiliency

Abstract

A 200 MSPS reconfigurable and blocker resilient analog-to-digital converter (ADC) is presented. The system consists of a discrete-time lossy differentiator frontend and a 6-bit noise shaping, pipeline ADC backend, which enables tolerance of a <;3 MHz narrowband blocker up to 40 dB stronger than the desired signal. Filtering in the presence of the blocker improves quantization by an additional 3 bits to accommodate the desired signal. With lower blocker power, the system defaults to Nyquist performance and an additional reconfiguration switch enables a 3-6 MHz, ΔΣ ADC. The system is designed in a 65 nm CMOS technology, has a total chip area of 1040 μm × 920 μm, and consumes 6.37 mW of power. Enabling blocker resilience improves the figure-of-merit (FOM) of the system from 474 fJ/lvl to 158 fJ/lvl.