A digital signal processor for low power

Abstract

Low power in digital signal processor design has been a critical design constraint since portable battery operated devices prevailed. Most of the power dissipation of a processor is in the clock network and the on-chip memory. By optimizing the critical path of the processor we could reduce the power of clock network. We propose an energy-efficient instruction set architecture to reduce the power consumption of the program memory access. We applied it to a digital hearing aid, and reduced the program memory size by approximately 75%.