{"title":"DLL based temperature compensated MEMS clock","authors":"A. Rantala, D. G. Martins, M. Sopanen, M. Åberg","doi":"10.1109/NORCHIP.2010.5669492","DOIUrl":null,"url":null,"abstract":"In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of − 40 to 85 °C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption. The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 µm standard CMOS process technology. The implementation occupies 1.75 mm2 of silicon area.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"NORCHIP 2010","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHIP.2010.5669492","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of − 40 to 85 °C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption. The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 µm standard CMOS process technology. The implementation occupies 1.75 mm2 of silicon area.