{"title":"A Low Power Diffused Bit Generator as a TRNG for Cryptographic Key Generation","authors":"D. Bharadwaj, P. Anirvinnan, B. S. Premanada","doi":"10.1109/DISCOVER52564.2021.9663619","DOIUrl":null,"url":null,"abstract":"Cryptographic key generation is an important part of the secured communication system where the key that is generated has a major role to play in the strength of the security of the data that is transferred. To enhance the necessary strength of the key, the random number generated has to be highly secure. This is enhanced by the use of a True Random Number Generation. Diffused Bit Generator (DBG) is an entropy source which is used to produce a sequence of random bits. It is composed of a Linear Feedback Shift Register (LFSR) and a Cellular Automata in order to increase the randomness emanating from the DBG. The proposed LFSR has been designed using TSPC based D flip-flops and the XOR gates consisting of 6 transistors, which has enabled to fulfil the objective of low power. The circuit implementation has been done in Cadence Virtuoso in the CMOS 180 nm technology and simulated in Cadence Spectre. The supply voltage used was 1.8 V and the circuits were simulated for the frequencies ranging from 100 MHz to 1 GHz and the proposed DBG was found to consume lesser power when compared to the existing architectures.","PeriodicalId":413789,"journal":{"name":"2021 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DISCOVER52564.2021.9663619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Cryptographic key generation is an important part of the secured communication system where the key that is generated has a major role to play in the strength of the security of the data that is transferred. To enhance the necessary strength of the key, the random number generated has to be highly secure. This is enhanced by the use of a True Random Number Generation. Diffused Bit Generator (DBG) is an entropy source which is used to produce a sequence of random bits. It is composed of a Linear Feedback Shift Register (LFSR) and a Cellular Automata in order to increase the randomness emanating from the DBG. The proposed LFSR has been designed using TSPC based D flip-flops and the XOR gates consisting of 6 transistors, which has enabled to fulfil the objective of low power. The circuit implementation has been done in Cadence Virtuoso in the CMOS 180 nm technology and simulated in Cadence Spectre. The supply voltage used was 1.8 V and the circuits were simulated for the frequencies ranging from 100 MHz to 1 GHz and the proposed DBG was found to consume lesser power when compared to the existing architectures.