A 140-MHz CMOS bit-level pipelined multiplier-accumulator using a new dynamic full-adder cell design

Abstract

A bit-level pipelined 12-b×12-b two's complement multiplier with a 27-b accumulator has been designed and fabricated in a 1-μm CMOS technology. A novel quasi N-P domino logic structure has been adopted to increase the throughput, and special pipeline structures were used to reduce the latency significantly. The measured maximum clock rate is 140 MHz (i.e. 140 million multiply-accumulate operations per second), and the typical power-speed ratio is 11 mW/MHz. The chip complexity is 10000 transistors and the 68-pad chip area is 2.5 mm×3.7 mm