Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only)

Abstract

Nonvolatile FPGAs (NV-FPGAs) have a potential advantage to eliminate wasted standby power which is increasingly serious in recent standard SRAM-based FPGAs. However, functionality of the conventional NV-FPGAs are not sufficient compared to that of standard SRAM-based FPGAs. For example, an effective circuit structure to perform shift-register (SR) function has not been proposed yet. In this paper, a magnetic tunnel junction (MTJ) based nonvolatile lookup table (NV-LUT) circuit that can perform SR function with low power consumption is proposed. The MTJ device is the best candidate in terms of virtually unlimited endurance, CMOS compatibility, and 3D stacking capability. On the other hand, large power consumption to perform SR function a serious design issue for the MTJ-based NV-LUT circuit. Since the write current for the MTJ device is large and all the data must be updated after the SR operation using CMOS-oriented method, large power consumption is indispensable. To overcome this issue, the address for read/write access is incremented at each cycle instead of direct data shifting in the proposed LUT circuit. In this way, the number of data update per 1-bit shift is minimized to one, which results in great power saving. Moreover, since the selector is shared both read (logic) and write operation, its hardware cost is small. In fact, 99% of power reduction and 52% of transistor counts reduction compared to those of SRAM-based LUT circuit are performed. The authors would like to acknowledge ImPACT of CSTI, CIES consortium program, JST-OPERA, and JSPS KAKENHI Grant No. 17H06093.