16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin

Abstract

Design and implementation of a novel 16-level multiple-valued memory is proposed. Each memory cell uses equivalent to one binary digit to detect the error due to leakage currents. Moreover, this feature increases the noise margin of the system by a factor of two. The refreshing circuitry is based on a series configuration of A/D and D/A converters for each data line. The error correction and storage scheme is based on a recently developed Multiple-Valued representation, calledContinuous Valued Number System (CVNS). This memory cell can be used in hardware implementation of multiple-valued neural networks based on the CVNS.