{"title":"Analogue weighted median filter based on cellular neural network for standard video signal processing","authors":"J. Kowalski","doi":"10.1109/CNNA.2002.1035106","DOIUrl":null,"url":null,"abstract":"A VLSI implementation of an analogue weighted median filter based on Cellular Neural Network (CNN) paradigm for standard video signal processing is described in this paper. This filter consists of feedforward nonlinear template B operating within the window of 3 by 3 pixels around the central pixel being filtered. The feedforward nonlinear coefficients are realized using a programmable nonlinear coupler circuits. Basic weighted median filter blocks and chip layout are presented. Technology applied for this implementation is CMOS AMS 0.8/spl mu/m CYE.","PeriodicalId":387716,"journal":{"name":"Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNNA.2002.1035106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A VLSI implementation of an analogue weighted median filter based on Cellular Neural Network (CNN) paradigm for standard video signal processing is described in this paper. This filter consists of feedforward nonlinear template B operating within the window of 3 by 3 pixels around the central pixel being filtered. The feedforward nonlinear coefficients are realized using a programmable nonlinear coupler circuits. Basic weighted median filter blocks and chip layout are presented. Technology applied for this implementation is CMOS AMS 0.8/spl mu/m CYE.