{"title":"Comparative performance analysis of gate-inside, gate-outside and gate-inside&outside cylindrical junctionless silicon nanotube FET","authors":"R. Ambika, R. Srinivasan","doi":"10.1109/ICICES.2017.8070771","DOIUrl":null,"url":null,"abstract":"In this paper, the performance investigation of Gate-Inside (GI), Gate-Outside (GO) cylindrical Junction-less Silicon Nanotube Field Effect Transistor (JLSiNT) devices and comparative analysis with Gate-Inside & Outside (GIO) JLSiNT device are done using 3D TCAD numerical simulations. ON current (I<inf>ON</inf>), OFF current (I<inf>OFF</inf>), Sub-threshold Swing (SS), Threshold voltage (V<inf>TH</inf>), Trans-conductance (g<inf>m</inf>), Output resistance (R<inf>OUT</inf>), Gate capacitance (C<inf>GG</inf>) and unity gain cutoff frequency (f<inf>T</inf>) are extracted for the above devices. For the matched I<inf>OFF</inf> scenario, GI shows better I<inf>ON</inf> but GO offers better f<inf>T</inf> since it has lower C<inf>GG</inf> comparatively. GIO device shows better SS and R<inf>OUT</inf> comparatively.","PeriodicalId":134931,"journal":{"name":"2017 International Conference on Information Communication and Embedded Systems (ICICES)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Information Communication and Embedded Systems (ICICES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICES.2017.8070771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, the performance investigation of Gate-Inside (GI), Gate-Outside (GO) cylindrical Junction-less Silicon Nanotube Field Effect Transistor (JLSiNT) devices and comparative analysis with Gate-Inside & Outside (GIO) JLSiNT device are done using 3D TCAD numerical simulations. ON current (ION), OFF current (IOFF), Sub-threshold Swing (SS), Threshold voltage (VTH), Trans-conductance (gm), Output resistance (ROUT), Gate capacitance (CGG) and unity gain cutoff frequency (fT) are extracted for the above devices. For the matched IOFF scenario, GI shows better ION but GO offers better fT since it has lower CGG comparatively. GIO device shows better SS and ROUT comparatively.