Design and implementation of reconfigurable IDCT architecture for multi-standard video decoders

Abstract

In this paper, we propose a reconfigurable IDCT architecture for multi-standard video decoders. It can support different video standards such as MPEG-1/2/4, VC-1 and H.264 AVC. Moreover, the particular part of this architecture does not use any multiplier and ROM circuit; it only needs adders and shifters. In digital circuit, the area of adders and shifters are superior to multipliers and ROM, The reconfigurable IDCT architecture only needs 13 adders in the adder kernel. Finally, we realize this architecture by using 0.18um technology to accomplish the chip design. The experimental result shows the total gate counts only 12.4 K. Moreover, the power consumption is 4.85mW@100MHz. Therefore, the architecture is regular and suitable for multi-standard video decoders.