{"title":"A Host Interface Architecture for HPPI","authors":"V. Kumar","doi":"10.1109/CMPCMM.1993.659093","DOIUrl":null,"url":null,"abstract":"Outline: Talk about the Architecture of the host interface for HIPPI and the performance results achieved. The talk includes the following: 1. Very breifly describe the architecture of a Node in the Paragon Supercomputer to point out that an interface is needed to: (a) Handle the requirements of the low-level HIPPI protocol. (b) Transfer data between the input/output channels of HIPPI and the host memory at the aggregate peak rate of 1.6 Gb/s. 2. (a) Describe the architecture of the host interface. (b) Show the data flow between the host memory and the input and output channels (c) Point out software design considerations for high performance. of HIPPI. 3. Discuss the performance results. Octobr 6.1993 Host Interface Architecture Performance results Reason for the Host Interface Requirements for an efficient algorithm","PeriodicalId":285275,"journal":{"name":"The 8th IEEE Workshop on Computer Communications","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 8th IEEE Workshop on Computer Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCMM.1993.659093","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Outline: Talk about the Architecture of the host interface for HIPPI and the performance results achieved. The talk includes the following: 1. Very breifly describe the architecture of a Node in the Paragon Supercomputer to point out that an interface is needed to: (a) Handle the requirements of the low-level HIPPI protocol. (b) Transfer data between the input/output channels of HIPPI and the host memory at the aggregate peak rate of 1.6 Gb/s. 2. (a) Describe the architecture of the host interface. (b) Show the data flow between the host memory and the input and output channels (c) Point out software design considerations for high performance. of HIPPI. 3. Discuss the performance results. Octobr 6.1993 Host Interface Architecture Performance results Reason for the Host Interface Requirements for an efficient algorithm