A very fast three-mode retiming PLL with low jitter and wide operating margin

H. Shirahama, K. Taniguchi, O. Tsukahara
{"title":"A very fast three-mode retiming PLL with low jitter and wide operating margin","authors":"H. Shirahama, K. Taniguchi, O. Tsukahara","doi":"10.1109/APCCAS.1994.514573","DOIUrl":null,"url":null,"abstract":"The proposed PLL realizes a fast and wide-ranging pull-in, and a stable locked condition by controlling a frequency difference detector and a PLL core with a dual loop constants in three modes. Simulations of the PLL designed with an 0.8 /spl mu/m bipolar devices and experiments using a PLL-IC together with PLAs demonstrated the features; a short pull-in time comparable to SAW filters even for 63 bit PRBS NRZ inputs, low output jitter and no slowly-recovering phase error.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.1994.514573","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

The proposed PLL realizes a fast and wide-ranging pull-in, and a stable locked condition by controlling a frequency difference detector and a PLL core with a dual loop constants in three modes. Simulations of the PLL designed with an 0.8 /spl mu/m bipolar devices and experiments using a PLL-IC together with PLAs demonstrated the features; a short pull-in time comparable to SAW filters even for 63 bit PRBS NRZ inputs, low output jitter and no slowly-recovering phase error.
一个非常快的三模重定时锁相环,具有低抖动和宽工作余量
该锁相环通过控制频率差检测器和具有双环常数的锁相环铁芯,在三种模式下实现了快速宽范围的拉入和稳定的锁相状态。采用0.8 /spl mu/m双极器件设计的锁相环的仿真和将锁相ic与PLAs结合使用的实验证明了该特性;即使对于63位PRBS NRZ输入,也可以与SAW滤波器相媲美的短拉入时间,低输出抖动,没有缓慢恢复的相位误差。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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