{"title":"Boost derived topology as a power factor correction circuit","authors":"A. Khan, I. Batarseh, K. Siri","doi":"10.1109/SECON.1994.324292","DOIUrl":null,"url":null,"abstract":"This paper proposes a novel PWM converter which is a modified version of the conventional boost topology with output electrical isolation and zero-voltage switching (ZVS). The steady-state analysis and the control characteristic curves are presented. Also, the authors present a closed loop system for the converter as a power factor correction circuit (PFCC) application. The system uses voltage referencing and current sensing. This is achieved by implementing the commercially available chip ML4821 (average current mode controller) in the closed loop system. Circuit simulation based on PSPICE of the proposed topology is given. It is shown that the simulation and theoretical results are in agreement.<<ETX>>","PeriodicalId":119615,"journal":{"name":"Proceedings of SOUTHEASTCON '94","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of SOUTHEASTCON '94","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SECON.1994.324292","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper proposes a novel PWM converter which is a modified version of the conventional boost topology with output electrical isolation and zero-voltage switching (ZVS). The steady-state analysis and the control characteristic curves are presented. Also, the authors present a closed loop system for the converter as a power factor correction circuit (PFCC) application. The system uses voltage referencing and current sensing. This is achieved by implementing the commercially available chip ML4821 (average current mode controller) in the closed loop system. Circuit simulation based on PSPICE of the proposed topology is given. It is shown that the simulation and theoretical results are in agreement.<>